`timescale  1ns/1ps

module tb_main();

glbl glbl();

reg  input_clk;
reg  sys_rst_n;

initial fork begin      //25M
  #3;
  input_clk = 1;
  forever begin
    #20;
    input_clk = ~input_clk;
  end
end
join

initial begin
    sys_rst_n  <= 1'b0;  
    #10
    sys_rst_n <= 1'b1;
    // $stop;
end      

top 
top_inst
(
  .input_clk(input_clk),     
  .sys_rst_n(sys_rst_n)  
);

endmodule
